The present invention generally relates to a method for fabricating semiconductor devices from a wafer level chip scale package and more particularly, relates to a method for fabricating semiconductor devices from a wafer level chip scale package that has discrete package encapsulation for minimizing coefficient of thermal expansion mismatch problems.
In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques of such high density devices. Conventionally, a flip-chip attachment method has been used in packaging of semiconductor chips. In the flip-chip attachment method, instead of attaching a semiconductor die to a lead frame in a package, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out in an evaporation method by using a composite material of tin and lead through a mask for producing a desired pattern of solder bumps. The technique of electrodeposition has been more recently developed to produce solder bumps in flip-chip packaging process.
Other techniques that are capable of solder-bumping a variety of substrates to form solder balls have also been proposed. The techniques generally work well in bumping semiconductor substrates that contain solder structures over a minimal size. For instance, one of such widely used techniques is a solder paste screening method which has been used to cover the entire area of an eight inch wafer. However, with recent trend in the miniaturization of device dimensions and the necessary reduction in bump-to-bump spacing (or pitch), the use of the solder paste screening technique has become impractical for several reasons. One of the problems in utilizing solder paste screening technique in bonding modern semiconductor devices is the paste composition itself. A solder paste is formed by a flux material and solder alloy particles. The consistency and uniformity of the solder paste composition become more difficult to control as the solder bump volume decreases. Even though a solution of the problem has been proposed by using solder paste that contain extremely small and uniform solder particles, it can only be achieved at a high cost penalty. A second problem in utilizing the solder paste screening technique in modern high density semiconductor devices is the available space between solder bumps. It is known that a large volume reduction occurs when a solder changes from a paste state to a cured stated, the screen holes for the solder paste must be significantly larger in diameter than the actual solder bumps to be formed. The large volume shrinkage ratio thus makes the solder paste screening technique difficult to carry out in high density devices.
Other techniques for forming solder bumps such as the controlled collapse chip connection (C4) technique and the thin film electrodeposition technique have also been used in recent years in the semiconductor fabrication industry. The C4 technique is generally limited by the resolution achievable by a molybdenum mask which is necessary for the process. Fine-pitched solder bumps are therefore difficult to be fabricated by the C4 technique. Similarly, the thin film electrodeposition technique which also requires a ball limiting metallurgy layer to be deposited and defined by an etching process which has the same limitations as the C4 technique. For instance, a conventional thin film electrodeposition process for depositing solder bumps is shown in FIGS. 1Axcx9c1F.
A conventional semiconductor structure 10 is shown in FIG. 1A. The semiconductor structure 10 is built on a silicon substrate 12 with active devices built therein. A bond pad 14 is formed on a top surface 16 of the substrate 12 for making electrical connections to the outside circuits. The bond pad 14 is normally formed of a conductive metal such as aluminum. The bond pad 14 is passivated by a final passivation layer 20 with a window 22 opened by a photolithography process to allow electrical connection to be made to the bond pad 14. The passivation layer 20 may be formed of any one of various insulating materials such as oxide, nitride or organic materials. The passivation layer 20 is applied on top of the semiconductor device 10 to provide both planarization and physical protection of the circuits formed on the device 10.
Onto the top surface 24 of the passivation layer 20 and the exposed top surface 18 of the bond pad 14, is then deposited an under bump metallurgy layer 26. This is shown in FIG. 1B. The under bump metallurgy (UBM) layer 26 normally consists of an adhesion/diffusion barrier layer 30 and a wetting layer 28. The adhesion/diffusion barrier layer 30 may be formed of Ti, TiN or other metal such as Cr. The wetting layer 28 is normally formed of a Cu layer or a Ni layer. The UMB layer 26 improves bonding between a solder ball to be formed and the top surface 18 of the bond pad 14.
In the next step of the process, as shown in FIG. 1C, a photoresist layer 34 is deposited on top of the UMB layer 26 and then patterned to define a window opening 38 for the solder ball to be subsequently formed. In the following electrodeposition process, a solder ball 40 is electrodeposited into the window opening 38 forming a structure protruded from the top surface 42 of the photoresist layer 34. The use of the photoresist layer 34 must be carefully controlled such that its thickness is in the range between about 30 xcexcm and about 40 xcexcm, preferably at a thickness of about 35 xcexcm. The reason for the tight control on the thickness of the photoresist layer 34 is that, for achieving a fine-pitched solder bump formation, a photoresist layer of a reasonably small thickness must be used such that a high imaging resolution can be achieved. It is known that, during a photolithography process, the thicker the photoresist layer, the poorer is the imaging process. To maintain a reasonable accuracy in the imaging process on the photoresist layer 34, a reasonably thin photoresist layer 34 must be used which results in a mushroom configuration of the solder bump 40 deposited therein. The mushroom configuration of the solder bump 40 contributes greatly to the inability of a conventional process in producing fine-pitched solder bumps.
Referring now to FIG. 1E, wherein the conventional semiconductor structure 10 is shown with the photoresist layer 34 removed in a wet stripping process. The mushroom-shaped solder bump 40 remains while the under bump metallurgy layer 26 is also intact. In the next step of the process, as shown in FIG. 1F, the UBM layer 26 is etched away by using the solder bump 40 as a mask in an wet etching process. The solder bump 40 is then heated in a reflow process to form solder ball 42. The reflow process is conducted at a temperature that is at least the reflow temperature of the solder material.
In recent years, chip scale packages (CSP) have been developed as a new low cost packaging technique for high volume production of IC chips. One of such chip scale packaging techniques has been developed by the Tessera Company for making a so-called micro-BGA package. The micro-BGA package can be utilized in an environment where several of the packages are arranged in close proximity on a circuit board or a substrate much like the arrangement of individual tiles. Major benefits achieved by a micro-BGA package are the combined advantages of a flip chip assembly and a surface mount package. The chip scale packages can be formed in a physical size comparable to that of an IC chip even though, unlike a conventional IC chip such as a flip chip, the chip scale package does not require a special bonding process for forming solder balls. Furthermore, a chip scale package may provide larger number of input/output terminals than that possible from a conventional quad flat package, even though a typical quad flat package is better protected mechanically from the environment.
To further reduce the fabrication cost of IC devices, it is desirable that if a whole wafer can be passivated to seal the IC dies on the wafer, and then be severed into individual IC dies from the wafer such that not only the benefits of a chip scale package can be realized, the packaging cost for the IC dies may further be reduced.
A large number of IC chips are designed with a peripheral array of I/O pads. For modern high density devices, the pitch allowed between I/O pads is steadily decreasing. An I/O pad redistribution process is frequently necessary for changing a peripheral array to an area array in order to improve pitch between the conductive pads. During the redistribution process, metal traces are frequently used to extend bond pads from a peripheral area to a center area on the chip. Due to the limited space available for the metal traces, especially those traces that run an extended distance, it is desirable to produce metal traces that are stress buffered in order to assure the reliability of a chip.
On a wafer level chip scale package, or a wafer level CSP, an insulating material layer that is frequently of polymeric base is used to encapsulate the entire wafer structure prior to the severing of individual chips from the wafer. The purpose of the encapsulation is to protect both mechanically and chemically the semiconductor devices fabricated on the wafer. To protect the devices mechanically means to shield the device from mechanical abrasion other damages during packaging of the device. To protect the devices chemically means to shield the device from moisture penetration and particulate contamination.
A typical wafer level CSP device 50 is shown in FIG. 2 in a partial, cross-sectional view. The device 50 is built on a silicon substrate 44 which has a plurality of bond pads 46 formed thereon. On top of the bond pads 46, is deposited an insulating material layer 48 such as an oxide layer. A metal conductive layer 52 is then deposited on top of the bond pads 46, the insulating material layer 48 and lithographically formed into input/output redistribution lines. On top of a distal end 54 of the I/O redistribution line is first coated with a thin layer of copper, and then formed a copper post 56, i.e. between 75xcx9c100 xcexcm, by filling a via opening with copper typically by a plating technique. A solder ball 58 is planted on top of the copper post 56 to complete the wafer level CSP process.
In the conventional structure 50, shown in FIG. 2, the thickness of the silicon substrate 44 is about 500 xcexcm, while the encapsulant layer 60 on top of the substrate 44 is about 100 xcexcm. Since the coefficient of thermal expansions of the two materials are different, i.e. the polymeric-based encapsulant 60 has a higher coefficients of thermal expansion than the silicon substrate 44. The mismatch between the coefficient of thermal expansion therefore leads to a significant warpage over the entire surface area of a wafer. The warpage problem is particularly severe in a large wafer such as in a 200 mm or in a 300 mm wafer.
Others have attempted to minimize or eliminate the warpage problem of the wafer level chip scale package caused by the thermal expansion differences described above. One method is to reduce the thickness of the encapsulant layer 60. However, when the thickness of the encapsulant layer 60 is reduced, the stand-off of the solder ball 58 from the silicon substrate 44 is also reduced. A reduced stand-off for the solder ball 58 can lead to other electrical problems such as solder ball cracking due to thermal stress after the package is mounted on the PCB.
Another attempt to reduce the warpage problem in wafer level chip scale package is shown in FIG. 3. Instead of the copper post 56 utilized in FIG. 2, solder balls 64, 66 are utilized in structure 62. The encapsulant layer 68 is dispensed on each die surface individually to create a discrete encapsulated wafer level CSP 62. After planarization of the encapsulated wafer surface, the package solder ball 66 is attached to the first solder ball 64. Even though a thinner die thickness and a larger standoff height are achieved, the process throughput is greatly reduced due to the added processing steps since the encapsulant layer must be dispensed on each die surface individually, and furthermore, the quality of encapsulation is difficult to control.
It is therefore an object of the present invention to provide a method for fabricating wafer level chip scale package with an encapsulant layer on top without the drawbacks or shortcomings of the conventional method.
It is another object of the present invention to provide a method for fabricating wafer level CSP with discrete package encapsulation.
It is a further object of the present invention to provide a method for fabricating wafer level CSP by forming islands of encapsulant with one island on top of each semiconductor die.
It is another further object of the present invention to provide a method for fabricating wafer level CSP with discrete package encapsulation formed by two different types of photoresist coatings on top of the wafer.
It is still another object of the present invention to provide a wafer level CSP that has a thick layer of encapsulant coated on top to minimize the coefficient of thermal expansion mismatch problem.
It is yet another object of the present invention to provide a wafer level CSP that has a plurality of trench openings formed on top of the wafer surface in-between a plurality of IC dies severing an encapsulant layer.
It is still another further object of the present invention to provide a method for fabricating wafer level CSP without coefficient of thermal expansion mismatch problem by first coating a dry film photoresist layer on top of the wafer followed by filling a plurality of trench openings over the scribe lines with a liquid photoresist material.
In accordance with the present invention, a method for fabricating wafer level chip scale package that has discrete package encapsulation and devices formed by the method are disclosed.
In a preferred embodiment, a method for fabricating a wafer level CSP with discrete package encapsulation can be carried out by the operating steps of providing a pre-processed wafer that has a first plurality of bond pads formed on top and a passivation layer formed in-between the pads; depositing a first conductive metal layer for I/O redistribution on top of the passivation layer and the first plurality of bond pads; depositing a first photoresist (PR) material forming a first PR layer on top of the first conductive metal layer; patterning the first PR layer to form a second plurality of trench openings each adapted to separate at least two IC chips and a third plurality of via openings each exposing the first conductive metal layer; depositing a second photoresist material and filling the second plurality of trench openings; filling the third plurality of via openings with a second conductive metal forming a third plurality of vias; removing the first PR material without disturbing the second PR material; lithographically forming I/O redistribution lines from the first conductive metal layer; forming an encapsulant layer on top of the I/O redistribution lines and embedding the second PR material and the third plurality of vias; planarizing the encapsulant layer, exposing top surfaces of the second PR material and the third plurality of vias; removing the second PR material forming a second plurality of trench openings dividing the IC chips into discrete packages; removing the first conductive metal layer in the second plurality of trench openings; and attaching a third plurality of solder balls on top of the third plurality of vias.
The method for fabricating a wafer level CSP with discrete package encapsulation may further include the step of depositing a dry film photoresist forming the first PR layer, or the step of depositing the second photoresist material in a liquid photoresist material. The method may further include the step of depositing the second photoresist material by a printing technique. The method may further include the step of filling the third plurality of via openings with at least one conductive metal selected from the group consisting of Au, Ag, Al, Cu and Ni. The method may further include the step of forming the encapsulant layer by a screen printing or stencil printing technique. The method may further include the step of filling the third plurality of via openings by an electroplating or an electroless plating technique. The method may further include the step of removing the second PR material by a wet stripping technique or by a dry stripping technique, or the step of removing the first conductive metal layer by wet etching, or the step of removing the first PR material by an etchant that has an etch rate toward the first PR material that is at least 5 times the etch rate toward the second PR material.
The present invention is further directed to a wafer level chip scale package which includes a wafer that has a first plurality of IC chips formed on a top surface; an insulating material layer overlying the plurality of IC chips; and a second plurality of trench openings formed in-between the first plurality of IC chips severing the insulating material layer.
The wafer level CSP may further include a third plurality of solder balls planted on each of the first plurality of IC chips. The insulating material layer may be an encapsulant layer. Each of the first plurality of IC chips forms a discrete island with an encapsulant layer on top. The second plurality of trench openings is formed along scribe lines between the first plurality of IC chips.
The present invention is still further directed to a method for fabricating wafer level chip scale package without coefficient of thermal expansion mismatch problem which can be carried out by the steps of providing a pre-processed wafer that has a first plurality of bond pads formed on top and a passivation layer formed in-between the pads; depositing a first conductive metal layer for I/O redistribution on top of the passivation layer and the first plurality of bond pads; depositing a dry film photoresist (PR) layer on top of the first conductive metal layer; patterning the dry film PR layer forming a second plurality of trench openings each adapted to separate at least two IC chips and a third plurality of via openings each exposing the first conductive metal layer; filling the second plurality of trench openings with a liquid photoresist material; filling the third plurality of via openings with a second conductive metal forming a third plurality of vias; stripping the dry film PR material without removing the liquid PR material; lithographically forming I/O redistribution lines from the first conductive metal layer; printing an encapsulant layer on top of the I/O redistribution lines embedding the liquid PR material and the third plurality of vias; removing the liquid PR material forming a second plurality of trench openings dividing the wafer into discrete packages; and planting a third plurality of solder balls on top of the third plurality of vias.
The method for fabricating wafer level CSP without coefficient of thermal expansion mismatch problem may further include the step of forming the third plurality of vias with at least one metal selected from the group consisting of Au, Ag, Al, Cu and Ni. The method may further include the step of filling the third plurality of via openings by an electroplating or an electroless plating technique. The method may further include the step of stripping the dry film photoresist by an etchant that has an etch selectivity larger than 5 toward the liquid photoresist material, or the step of filling the second plurality of trench openings by a screen printing or a stencil printing technique.